HBM: High-Bandwidth Memory
HBM is stacked DRAM placed next to the GPU die on the same package and connected by a very wide interface, giving several terabytes per second of memory bandwidth. Data-center accelerators use HBM instead of GDDR because model weights and activations demand extreme bandwidth.
HBM stacks multiple DRAM dies vertically and links them to the processor through thousands of connections over a silicon interposer. That very wide bus delivers memory bandwidth far above GDDR or standard DDR, which is what large-model training and HPC need to keep compute units fed. Successive generations, HBM2e, HBM3, and HBM3e, raise both capacity per stack and bandwidth.
Bandwidth, not just capacity, is the point. A GPU can hold billions of parameters, but throughput stalls if memory cannot feed the cores fast enough. HBM keeps the arithmetic units busy on memory-bound workloads like transformer training and large-batch inference. It is also power efficient per bit moved compared to driving signals across a board to separate memory chips.
For buyers, HBM capacity per GPU sets the largest model or batch that fits without splitting across cards, and total HBM bandwidth often predicts real training throughput better than raw compute numbers. When comparing accelerators from China, check the exact HBM generation, capacity, and bandwidth of the specific SKU rather than trusting the model family name.
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