ECC memory: Error-Correcting Code
ECC memory is RAM that detects and corrects single-bit errors and detects multi-bit errors using extra parity bits. It prevents silent data corruption and crashes from cosmic-ray bit flips, which is why it is standard in servers and required for reliable 24/7 operation.
Standard ECC adds an extra DRAM chip per rank to store check bits, typically using a SECDED scheme that corrects any single-bit error and detects any double-bit error. When a bit flips from radiation or electrical noise, the controller repairs it transparently and logs the event, so the workload keeps running without corrupted data.
Servers extend this with features like Dell SDDC or memory mirroring that survive an entire failed DRAM chip. ECC requires support from both the CPU memory controller and the DIMM, and server RDIMMs and LRDIMMs include it by default. Desktop UDIMMs usually do not.
For any server bought from China that will run production workloads, ECC is not optional. Check that the memory modules are ECC-rated and that the BMC logs correctable errors, which give early warning of a failing DIMM before it causes an outage.
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