Memory channels & DIMM population
A memory channel is an independent path between the CPU and its DIMMs. Total bandwidth scales with the number of populated channels, so filling every channel matters more than filling every slot. Modern Xeon and EPYC CPUs have 8 or more channels per socket.
Memory bandwidth is roughly the channel count multiplied by the per-channel speed, so a CPU runs fastest when all its channels carry at least one DIMM. Intel Ice Lake and Sapphire Rapids Xeons use 8 channels per socket, AMD EPYC Rome and Milan use 8, and EPYC Genoa uses 12. Leaving channels empty leaves bandwidth on the table.
Most platforms provide two DIMM slots per channel. Filling only the first slot of every channel (one DIMM per channel) usually gives the highest supported speed, while filling both slots (two DIMMs per channel) can force a lower speed on some generations. Balanced, symmetric population across all channels is required for peak performance.
When configuring a server from China, prioritize populating every channel over stacking many DIMMs on a few channels. For example, on a 12-channel EPYC Genoa, twelve 32 GB modules beat six 64 GB modules for bandwidth-sensitive workloads even at the same total capacity. Ask the supplier to populate memory symmetrically.
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